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The high duty cycle is given by Equation 19.5 (p. 255)
TIMER Up-count Duty Cycle Equation
DS up = CCVx/TOP
(19.5)
19.3.2.7 Up/Down-count (Dual-slope) PWM
If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual
slope PWM output will be generated by Figure 19.19 (p. 255) .The resolution (in bits) is given by
Equation 19.6 (p. 255) .
Figure 19.19. TIMER Up/Down-count PWM Generation
TIMERn_TOP
TIMERn_CCx_CCV
0
TIMn_CCx
Overflow
Com pare m atch
Buffer update
TIMER Up/Down-count PWM Resolution Equation
R PWM up/down = log(TOP+1)/log(2)
The PWM frequency is given by Equation 19.7 (p. 255) :
TIMER Up/Down-count PWM Frequency Equation
f PWM up/down = f HFPERCLK / ( 2^(PRESC+1) x TOP)
The high duty cycle is given by Equation 19.8 (p. 255)
TIMER Up/Down-count Duty Cycle Equation
DS up/down = CCVx/TOP
(19.6)
(19.7)
(19.8)
19.3.3 Dead-Time Insertion Unit (TIMER0 only)
The Dead-Time Insertion Unit aims to make control of BLDC motors safer and more efficient
by introducing complementary PWM outputs with dead-time insertion and fault handling, see
Figure 19.20 (p. 255) .
Figure 19.20. TIMER Dead-Time Insertion Unit Overview
Original PWM (TIM0_CCx_pre)
Dead tim e
insertion
Fault
handling
Prim ary output (TIM0_CCx)
Com plem entary output (TIM0_CDTIx)
Fault sources
When used for motor control, the PWM outputs TIM0_CC0, TIM0_CC1 and TIM0_CC2 are often
connected to the high-side transistors of a triple half-bridge setup (UH, VH and WH), and the
2011-04-12 - d0001_Rev1.10
255
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